Multiple-Valued Logic Minimization for PLA Synthesis
- 5 June 1986
- report
- Published by Defense Technical Information Center (DTIC)
Abstract
Multiple-valued logic minimization is an important technique for reducing the area required by a Programmable Logic Array (PLA). This report describes both heuristic and exact algorithms for solving the multiple-valued logic minimization problem. These algorithms have been implemented in a C program called Espresso-MV.Keywords
This publication has 0 references indexed in Scilit: