Establishing a tight bound on task interference in embedded system instruction caches

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Abstract
To help meet the increasing performance demands of embedded applications, caches are utilized in some embedded systems. However, caches are problematic in real-time systems because they may cause a task's execution time to be uncertain, making a tight worst-case time-bound difficult to achieve. To simplify an execution time analysis, conservative assumptions are often made that may waste system capability or lead to an unnecessarily costly system. Efficient system design requires methods to tightly bound the effect of complex cache behavior.This paper presents methods that bound the effect of sharing an instruction cache among multiple tasks. If an application is interrupted, the intervening task often changes cache state - so the application experiences degraded performance when it resumes. Techniques that tightly bound this effect are the goal of this paper.Our methodology uses the concept of a "live cache frame," a cache frame that contains a block that is accessed in the future and without an intervening eviction. An intervening task delays the completion of an application both by its execution time and by evicting blocks from the application's live frames (LRU status changes have a secondary effect). Only these evictions cause future misses that would not otherwise occur. The maximum number of live frames coexistent during the execution of an application bound such misses, independent of intervening tasks. This is central to one method presented. We also present methods that exploit knowledge of the character of an intervening task to achieve a tighter bound when possible.

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