Heuristic Synthesis of Microprogrammed Computer Architecture

1 August 1974

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-23 (8) , 802-807
https://doi.org/10.1109/t-c.1974.224036

Abstract

This paper describes an algorithm for the synthesis of applications-oriented microcode for a dynamically microprogrammable computer. The synthesis algorithm provides an iterative method for generating specialized architectures. Current attempts at generating specialized architectures can be considered as manual tuning due to human generation of specialized microcode. Heuristic instruction synthesis is described as one phase of a heuristic tuning process which attempts to automate the manual tuning process.

Keywords

This publication has 6 references indexed in Scilit:

A Data Base For Computer Performance Evaluation
Computer, 1973
Optimization Strategies for Microprograms
IEEE Transactions on Computers, 1971
Dynamic microprogramming
Communications of the ACM, 1971
On the Minimization of READ-ONLY Memories in Microprogrammed Digital Computers
IEEE Transactions on Computers, 1970
System Design of a Dynamic Microprocessor
IEEE Transactions on Computers, 1970
A formal semantics for computer languages and its application in a compiler-compiler
Communications of the ACM, 1966