A VLSI array architecture for the on-line training of recurrent neural networks

Publisher Website

9 December 2002

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 506-510
https://doi.org/10.1109/acssc.1991.186501

Abstract

No abstract available

Keywords

This publication has 1 reference indexed in Scilit:

A unified systolic architecture for artificial neural networks
Journal of Parallel and Distributed Computing, 1989