Self Aligned Radiation Hard CMOS/SOS
- 1 December 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 23 (6) , 1610-1612
- https://doi.org/10.1109/tns.1976.4328549
Abstract
This paper reports the results of extending previously reported radiation hardening methods to a self-aligned CMOS/SOS process. Over 20 lots of CMOS/SOS circuits have been fabricated with this process. Threshold shifts, after 1 Mrad (Si) Co60 irradiation are ≤ 1.2V for the n-channel devices and ≤ 2.7V for the p-channel devices under worst case bias conditions. Several lots of devices have been fabricated with μ 0.7V n-channel shifts and ≤ 1.2V p-channel shifts under the above radiation and bias conditions. Post-irradiation n-channel back leakage is in the range of .05 to 5 μA per mil of channel width, the specific value dependent to a considerable extent on quality of the starting SOS material. Electrical parameters and life-test stability are excellent and equal to those obtained with similar, non-radiation-hard processes.Keywords
This publication has 4 references indexed in Scilit:
- Effects of Defects and Impurities in Starting Material on Radiation Hardness of CMOS/SOS DevicesIEEE Transactions on Nuclear Science, 1976
- Radiation Hardened CMOS/SOSIEEE Transactions on Nuclear Science, 1975
- Investigation of Radiation Effects and Hardening Procedures for CMOS/SOSIEEE Transactions on Nuclear Science, 1975
- Process Optimization of Radiation-Hardened CMOS Integrated CircuitsIEEE Transactions on Nuclear Science, 1975