Floating well based design methodology aimed to improve latch-up immunity in a smart power technology
- 30 September 1992
- journal article
- Published by Elsevier in Microelectronic Engineering
- Vol. 19 (1-4) , 161-164
- https://doi.org/10.1016/0167-9317(92)90414-m
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- The smart power high-side switch: description of a specific technology, its basic devices, and monitoring circuitriesIEEE Transactions on Electron Devices, 1990
- DC holding and dynamic triggering characteristics of bulk CMOS latchupIEEE Transactions on Electron Devices, 1983
- Influence of the floating substrate potential on the characteristics of ESFI MOS transistorsSolid-State Electronics, 1975