Parallel VLSI architecture for MAP turbo decoder
- 27 August 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 384-388
- https://doi.org/10.1109/pimrc.2002.1046727
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
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- Optimized MAP turbo decoderPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
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- VLSI architectures for turbo codesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1999
- Near optimum error correcting coding and decoding: turbo-codesIEEE Transactions on Communications, 1996