Comparison of floating gate neural network memory cells in standard VLSI CMOS technology
- 1 May 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Neural Networks
- Vol. 3 (3) , 347-353
- https://doi.org/10.1109/72.129407
Abstract
Several floating gate MOSFET structures, for potential use as analog memory elements in neural networks, have been fabricated in a standard 2 mum double-polysilicon CMOS process. Their physical and programming characteristics are compared with each other and with similar structures reported in the literature. None of the circuits under consideration require special fabrication techniques. The criteria used to determine the structure most suitable for neural network memory applications include the symmetry of charging and discharging characteristics, programming voltage magnitudes, the area required, and the effectiveness of geometric field enhancement techniques. This work provides a layout for an analog neural network memory based on previously unexplored criteria and results. The authors have found that the best designs (a) use the poly1 to poly2 oxide for injection; (b) need not utilize ;field enhancement' techniques; (c) use poly1 to diffusion oxide for a coupling capacitor; and (d) size capacitor ratios to provide a wide range of possible programming voltages.Keywords
This publication has 19 references indexed in Scilit:
- Analog floating-gate synapses for general-purpose VLSI neural computationIEEE Transactions on Circuits and Systems, 1991
- A floating-gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS processIEEE Electron Device Letters, 1991
- Flash memories: the best of two worldsIEEE Spectrum, 1989
- Analog electronic neural network circuitsIEEE Circuits and Devices Magazine, 1989
- An electrically trainable artificial neural network (ETANN) with 10240 'floating gate' synapsesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- An analog trimming circuit based on a floating-gate deviceIEEE Journal of Solid-State Circuits, 1988
- A novel floating-gate method for measurement of ultra-low hole and electron gate currents in MOS transistorsIEEE Electron Device Letters, 1986
- A 16K E/SUP 2/PROM employing new array architecture and designed-in reliability featuresIEEE Journal of Solid-State Circuits, 1982
- On tunneling in metal-oxide-silicon structuresJournal of Applied Physics, 1982
- Fowler-Nordheim Tunneling into Thermally Grown SiO2Journal of Applied Physics, 1969