A redundant multi-valued logic for 10 Gb/s CMOS demultiplexer IC

13 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 220-221,
https://doi.org/10.1109/isscc.2001.912612

Abstract

A redundant multi-valued logic is used in >Gb/s communication lC applications. Using this logic, a quadruple data rate demultiplexer (serial-parallel converter) IC in 0.18 /spl mu/m CMOS achieves 10 Gb/s operation with 1.3 V supply and 38 mW consumption.

Keywords

MULTIVALUED LOGIC
CMOS INTEGRATED CIRCUITS
CLOCKS
TIMING
CMOS LOGIC CIRCUITS
LOGIC TESTING
PHASE LOCKED LOOPS
SEMICONDUCTOR DEVICE MEASUREMENT
FREQUENCY
VOLTAGE

This publication has 1 reference indexed in Scilit:

A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links
IEEE Journal of Solid-State Circuits, 1996