A 64K DRAM with 35 ns static column operation
- 1 October 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 18 (5) , 447-451
- https://doi.org/10.1109/JSSC.1983.1051976
Abstract
A 64K dynamic RAM with a function mode similar to static memory operation is described. The device has multiplexed address inputs and a one-address strobe clock (RAS). After a row address is applied to the device, column selection is performed as in static memory, resulting in fast cycle time and simplicity of use. Column address access time and cycle times of 35 ns are achieved. The device has some other functions to reduce critical timings. Address transition detector circuits are used for column selection. An improved column decoder is provided to allow column address input skew. The device uses NMOS single transistor memory cells and is packaged in a standard 300-mil 16-pin DIP.Keywords
This publication has 4 references indexed in Scilit:
- A 100ns 64K dynamic RAM using redundancy techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- A 100 ns 5 V only 64Kx1 MOS dynamic RAMIEEE Journal of Solid-State Circuits, 1980
- Soft error improvement of dynamic RAM with Hi-C structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- The Hi-C RAM cell conceptIEEE Transactions on Electron Devices, 1978