Self-Timed FIFO: An Exercise in Compiling Programs into VLSI Circuits
Open Access
- 1 January 1986
- report
- Published by Defense Technical Information Center (DTIC)
Abstract
A method for compiling a high-level description of a computation (a set of communicating processes) into a self-timed VLSI circuit is explained with an example: the construction of a self-timed FIFO element. The method essentially relies on the four-phase handshaking expansion of the communication actions. The program of each process is compiled into a set of production rules from which all explicit sequencing has been removed. By matching the production rules to those describing the semantics of the VLSI-operators (an d- gate, or-gate, C-element, arbiter, etc.), the programs are identified with networks of operators. We show how the different heuristics that the method allows lead to different circuits. In particular, the example illustrates the trade-offs between simplicity and efficiency of the circuits.Keywords
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