Study of the switching performance of a power MOSFET circuit

1 June 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 02759306,p. 215-224
https://doi.org/10.1109/pesc.1984.7083483

Abstract

Extremely short switching times can be achieved by using a power MOSFET. This paper deals with the electrical stress of power MOS devices, caused by short switching times in a circuit with parasitic network parameters and device parameters. The switching behaviour is studied theoretically as well as experimentally. The most familiar types of power MOSFETs implies a pn-diode as well as a blocked npn-transistor. The experimental part of this work studies the influence of this parasitic bipolar transistor (PBT) during commutation. The critical values of di/dt and du/dt are shown. For the theoretical investigations of the switching behaviour, the power MOSFET has been replaced by a suitable equivalent circuit with values only being given in standard data sheets. The nonlinear FET capacitances as well as the charge stored in the freerunning diode are taken into consideration.

Keywords

This publication has 0 references indexed in Scilit: