An experimental multiplier circuit based on superconducting Josephson devices
- 1 October 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 10 (5) , 360-368
- https://doi.org/10.1109/jssc.1975.1050624
Abstract
This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-/spl mu/m minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 /spl mu/W per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.Keywords
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