Prefetch unit for vector operations on scalar computers
- 1 September 1992
- journal article
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 20 (4) , 31-37
- https://doi.org/10.1145/142880.142891
Abstract
Current caches are not adequate for vector operations. A new kind of support for vector operations, called prefetch unit, is designed to improve the performance of the scalar (SISD) processors. The prefetch unit can be used for any SISD architecture and also for many kinds of MIMD architectures. It may run in parallel and asynchronously with other parts of processor. It keeps trace of the history of memory references, and therefore initializes rarely any superfluous prefetches.Keywords
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