A digital-serial silicon compiler
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 646-649
- https://doi.org/10.1109/dac.1988.14834
Abstract
A novel silicon compiler is described, called PARSIFAL. It constructs chips with a data-flow architecture in which data is passed in a digit-wide pipeline form one computational element to the next. The size of a digit can be specified by the user to be any value between one and the full word size of the chip. A digit size of one gives bit-serial chips, whereas a digit-size equal to the word-size gives fully parallel computation. It is shown that an intermediate value of the digit-size usually gives the most efficient chips in terms of throughput per unit area.Keywords
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