Inherent pattern jitter of STM-64 format signal and a reduction method

22 October 1992

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 28 (22) , 2110-2112
https://doi.org/10.1049/el:19921353

Abstract

The inherent pattern jitter of the STM-64 format signal is found to be increased by the DC level fluctuation of incoming data and the output power variation of the timing tank in the section overhead bytes which become longer than the time constant of the timing tank. This pattern jitter is reported to be success fully suppressed by using an already proposed timing recovery circuit with a 1/2T differentiator, which operates as a pattern transformer.

Keywords

PATTERN TRANSFORMER
TIME CONSTANT
SECTION OVERHEAD BYTES
TIMING TANK
DC LEVEL FLUCTUATION
TIMING RECOVERY CIRCUIT
PATTERN JITTER
JITTER SUPPRESSION
SYNCHRONOUS TRANSPORT MODULE
STM-64 FORMAT SIGNAL
JITTER REDUCTION
1/2T DIFFERENTIATOR
OUTPUT POWER VARIATION

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