A superscalar RISC processor with pseudo vector processing feature
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 102-109
- https://doi.org/10.1109/iccd.1995.528797
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
- An Efficient Architecture For Loop Based Data PreloadingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Pseudo vector processor based on register-windowed superscalar pipelinePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 120-MHz BiCMOS superscalar RISC processorIEEE Journal of Solid-State Circuits, 1994
- Evaluation of pseudo vector processor based on slide-windowed registersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1994
- A scalar architecture for pseudo vector processing based on slide-windowed registersPublished by Association for Computing Machinery (ACM) ,1993
- High-bandwidth data memory systems for superscalar processorsPublished by Association for Computing Machinery (ACM) ,1991
- Software prefetchingPublished by Association for Computing Machinery (ACM) ,1991