A high performance 50 nm PMOSFET using decaborane (B/sub 10/H/sub 14/) ion implantation and 2-step activation annealing process

23 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01631918,p. 471-474
https://doi.org/10.1109/iedm.1997.650426

Abstract

A high performance 50 nm PMOSFET with 7-nm-deep ultra shallow junction is described. Ultra-low energy implantation of B/sub 10/H(14/sup +/) at 2 keV (effective energy of boron is 0.2 keV) which never causes transient enhanced diffusion (TED) is utilized for the extension formation. To prevent thermal diffusion (TD), we developed a 2-step activation annealing process (2-step AAP) which forms a shallow extension with a low temperature annealing after the deep source/drain (S/D) formation. The highest drive current of 0.40 mA/um (@I/sub off/ of 1 nA/um and V/sub d/=-1.8 V) which improves 15% as compared with published data is achieved. The smallest PMOSFET with a L/sub eff/ of 38 nm is demonstrated for the first time. A low S/D series resistance R/sub sd/ of 760 ohm-um is achieved even if using a high sheet resistance (>20 Kohm/sq) for the extension regions due to the diminished extension length.

Keywords

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