Ultra-large scale integration

1 November 1984

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 31 (11) , 1555-1561
https://doi.org/10.1109/t-ed.1984.21752

Abstract

Ultra-large scale integration is governed by a hierarchical matrix of limits. The levels of this hierarchy can be codified as 1) fundamental, 2) material, 3) device, 4) circuit, and 5) system. Each level includes both theoretical and practical as well as analogical limits. Theoretically, thermal fluctuations impose a fundamental limit of several kT on switching energy. Scattering limited velocity and critical electric field establish a material limit on switching speed. Avoidance of punchthrough sets a device dimension limit. CMOS power-delay product defines a circuit limit. And, clock skew represents a system limit on ULSI. For conservative design margins, circuit limits project MOSFET channel lengths in the 0.4-0.2 µm range.

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