A process simulation model for multilayer structures involving polycrystalline silicon
- 1 November 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 29 (11) , 1726-1734
- https://doi.org/10.1109/t-ed.1982.21017
Abstract
The increasing complexity of VLSI fabrication often requires the use of multilayer structures above the silicon substrate. Electrical and metallurgical properties of multilayer structures have an important effect on circuit performance and reliability. Although process simulation models are available and widely used for computer-aided process design, none of the existing process simulation programs have the capability for modeling multilayer structures. A new model with such capability has been developed and this paper presents the physics as well as the results of simulation supported by experimental data. The model can simulate many desirable properties of multilayer structures involving polycrystalline silicon, such as grain growth, resistivity and oxidation rate of the polysilicon layer, the impurity redistribution across multilayers after high-temperature thermal processing, impurity segregation both at grain boundaries and at interfaces, and the interdependent phenomena of dopant-dependent oxidation/diffusion.Keywords
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