Avalanche breakdown in high-voltage D-MOS devices
- 1 January 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 23 (1) , 1-4
- https://doi.org/10.1109/t-ed.1976.18337
Abstract
A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n+drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n+region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.Keywords
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