An optimal floating-point pipeline CMOS CORDIC processor
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 2043-2047 vol.3
- https://doi.org/10.1109/iscas.1988.15343
Abstract
The authors present a VLSI CORDIC processor which is obtained using the hierarchical and interactive design methodology on which the DELFT VLSI synthesis is built. They also present an optimized (floating-point) CORDIC algorithm, the hierarchical mapping of this algorithm on a floating-point architecture, the design method, the layout, the chip, and its performance. Algorithm, architecture, and layout are parameterized with respect to the accuracy of rotation angles and vectors. The CORDIC chip is a pipeline that performs 10/sup 7/ plane rotations/s and is mounted in a 144-pin package. The vector entries are 21 bit floating-point numbers (16-bit mantissa and 5 bit exponent in twos complement).Keywords
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