A method is described by which switched-capacitor filters employing voltage invertor switches can be designed using a two-phase clock. The resulting circuits are completely insensitive to bottom plate parasitics and the operating rate of the amplifiers is only twice the operating rate of the filter so that this method is suitable for higher clock frequency applications. Furthermore, the SC filters have low attenuation sensitivity to element variations, due to the one-to-one correspondence between the capacitors and the elements of the reference filter and owing to the fact that no matching is required between the network capacitors and the auxiliary hold capacitors.