VLSI Implementation of a linear systolic array

Publisher Website

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/icassp.1985.1168228

Abstract

No abstract available

Keywords

This publication has 3 references indexed in Scilit:

Experience with the CMU Programmable Systolic Chip
Published by Springer Nature ,1985
A highly concurrent algorithm and pipeleined architecture for solving Toeplitz systems
IEEE Transactions on Acoustics, Speech, and Signal Processing, 1983
Advances in mathematical models for image processing
Proceedings of the IEEE, 1981