Derivation of Minimum Test Sets for Unate Logical Circuits

1 November 1971

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-20 (11) , 1264-1269
https://doi.org/10.1109/t-c.1971.223126

Abstract

A derivation of test sets S0and S1for irredundant unate logical circuits is presented. It is shown that these sets (S0and S1, respectively) detect all stuck-at-0 and stuck-at-1 faults in all realizations with no internal inverters of a given unate function. They can be obtained easily from the minimum sum and minimum product forms, from a Karnaugh map, or from a Hasse diagram of the function. These sets are minimum in the sense that there is no set with a smaller number of elements that detects all faults in the class of realizations of a logical function. In particular, it is found that a two-level AND–OR (OR–AND) network needs all the tests in S0(S1).

Keywords

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