A 1.5ns, 64kb ECL-CMOS SRAM

• 1 January 1991
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• p. 11-12
• https://doi.org/10.1109/vlsic.1991.760054

Abstract

Keywords

• RANDOM ACCESS MEMORY
• READ-WRITE MEMORY
• VOLTAGE
• BICMOS INTEGRATED CIRCUITS
• DELAY EFFECTS
• DRIVER CIRCUITS
• BIPOLAR TRANSISTORS
• SWITCHES
• PARASITIC CAPACITANCE
• LABORATORIES