Mappable peripheral memory for high speed applications
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1/56-1/58
- https://doi.org/10.1109/cmpeur.1989.93344
Abstract
A 30-ns mappable peripheral memory subsystem called MAP, is described. The MAP significantly enhances system performance by integrating, on the same chip, a 128-kb EPROM for program storage, a SRAM for data storage, and a programmable mapping decoder (PMD) for address decoding and mapping. The PMD is integrated into the memory-decode logic without adding up the access time. The decoder facilitates address mapping within a 2-Mb address space. The MAP is ideally suited as an expansion peripheral memory for high-speed digital signal processors, microprocessors, and microcontrollers. The 290-mil-sq. chip is implemented in a 1.2- mu m CMOS EPROM process.<>Keywords
This publication has 1 reference indexed in Scilit:
- A 50-ns 256 K CMOS split-gate EPROMIEEE Journal of Solid-State Circuits, 1988