A Cooperative Highly-available Multi-processor Architecture CHAMP

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Abstract
This paper describes a research effort to design and construct a computer hardware architecture capable of expanding to accommodate additional processing needs and sustaining massive hardware failures while still retaining a useable processing ability. The SRI proprietary architecture described here has been developed to use a large number of processors in an arbitrarily connected lattice. This architecture is called CHAMP for Cooperative Highly Available Multi-Processor. The reasoning behind, and the justification for, such a design is explored. CHAMP will to be programmed using a design methodology based on the M-module (model-driven module), which is an autonomous pro- reduction of components and pin count gram module containing a model, a set of values, and a set of procedures. The use of this methodology is explored along with its application to fault tolerance. Basic fault tolerance algorithms are described in relation to the CHAMP architecture. Hardware has been designed and constructed for an initial test of the concepts.

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