A high performance 0.5 mu m BiCMOS triple polysilicon technology for 4 Mb fast SRAMs
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 481-484
- https://doi.org/10.1109/iedm.1990.237063
Abstract
A high-performance 0.5 mu m BiCMOS technology has been developed which uses a triple polysilicon process architecture for a 4 Mb fast SRAM class of products. Three layers of polysilicon are used to achieve a compact four transistor cell size that is less than 20 mu m/sup 2/ by creating self-aligned bit-sense and Vss contacts to the four transistor cell. A WSi/sub x/ polycide emitter n-p-n transistor has been implemented with an emitter area of 0.8*2.4 mu m/sup 2/ and peak cutoff frequency (f/sub T/) of 14 GHz. A selectively ion implanted collector has been used to compensate the base channeling tail as well as to increase knee current and f/sub T/, while maintaining a collector to emitter breakdown voltage of 6.5 V. A minimum ECL gate delay of 115 ps has been achieved at a gate current of 400 mu A.Keywords
This publication has 1 reference indexed in Scilit:
- A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantationIEEE Transactions on Electron Devices, 1989