Partially-depleted SOI technology for digital logic

20 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 426-427
https://doi.org/10.1109/isscc.1999.759337

Abstract

This partially-depleted (PD) silicon on insulator (SOI) technology results in 20-35% performance gain over a comparable bulk technology. A number of SOI-unique effects that complicate device and circuit design are discussed, along with possible remedies. A fully functional 32 bit microprocessor, operating at >500 MHz, demonstrates this SOI technology.

Keywords

MICROPROCESSORS
CMOS TECHNOLOGY
UNCERTAINTY
FREQUENCY
CMOS LOGIC CIRCUITS
PHASE LOCKED LOOPS
OPERATING SYSTEMS
PERFORMANCE GAIN
HISTORY
DELAY EFFECTS

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