A Radiation-Hard Silicon Gate Bulk CMOS Cell Family

1 January 1980

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 27 (6) , 1712-1715
https://doi.org/10.1109/TNS.1980.4331093

Abstract

A radiation-hardened silicon gate CMOS two-port standard cell family utilizing a linear array layout topology with six to seven micron design rules and guardbanded n-channel devices has been developed. The process, structure, performance, and applications of this Expanded Linear Array (ELA) technology are described.

Keywords

SILICON
IMPLANTS
LABORATORIES
CMOS TECHNOLOGY
STANDARDS DEVELOPMENT
ROUTING
ALUMINUM
INTEGRATED CIRCUIT INTERCONNECTIONS
THRESHOLD VOLTAGE
ETCHING

This publication has 2 references indexed in Scilit:

Methods for Hierarchical Automatic Layout of Custom LSI Circuit Masks
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1978
Process Optimization of Radiation-Hardened CMOS Integrated Circuits
IEEE Transactions on Nuclear Science, 1975