Proposal for a versatile monolithic multi-Gbit/s m-sequence test system

13 September 1990

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 26 (19) , 1625-1626
https://doi.org/10.1049/el:19901041

Abstract

A multi-functional system is proposed which combines four important features for m-sequence applications: Generation of m-sequences, detection of bit errors, derivation of word synchronisation pulses, and scrambling as well as descrambling of a data stream. Circuit simulations show that a monolithic realisation for data rates of more than 10Gbit/s is feasible using a simple self-aligning Si bipolar technology.

Keywords

SEMICONDUCTORS
SIMPLE SELF-ALIGNING SI BIPOLAR TECHNOLOGY
10 GBIT/S
DETECTION OF BIT ERRORS
DERIVATION OF WORD SYNCHRONISATION PULSES
SCRAMBLING
FEATURES
MAXIMUM LENGTH SEQUENCE GENERATOR
PSEUDORANDOM BINARY SEQUENCE GENERATOR
MONOLITHIC REALISATION
MULTI-GBIT/S M-SEQUENCE TEST SYSTEM
SI CIRCUITS
DESCRAMBLING
MULTI-FUNCTIONAL SYSTEM
M-SEQUENCE GENERATION

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