A Novel Parallel Binary Counter Design with Parity Prediction and Error Detection Scheme

1 January 1971

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-20 (1) , 44-48
https://doi.org/10.1109/t-c.1971.223080

Abstract

In binary counters, the parity bit is not preserved when the data undergo the counting operation. It is necessary to predict the parity bit that should be used with the correct result. A special design has been devised to share as much hardware as possible between the counter and the parity prediction circuit. This reduces the number of logic gates and gives a more efficient design. The scheme involves the use of the first 0 detection for both the counting operation and the parity prediction.

Keywords

LOGIC
SCHEME
PARITY
CIRCUIT
BIT
BINARY COUNTERS
DEVISED
UNDERGO

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