A 1.5-ps Josephson OR gate

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 884-885
https://doi.org/10.1109/iedm.1988.32952

Abstract

A high-speed performance of a Josephson MVTL (modified variable threshold logic) OR gate was demonstrated. This fast operation was achieved by miniaturizing the gate. An MVTL gate fabricated with Nb/AlO/sub x//Nb Josephson junctions, SiO/sub 2/ insulators and Mo resistors is shown. The Josephson critical current, I/sub c/, is proportional to the junction size, so when the size is reduced, the increased I/sub c/ spread is crucial in operating many junctions at the same bias current. The maximum-to-minimum spread in I/sub c/ for 100 gates connected in series was +or-6% of the mean. This small spread was achieved by reducing the thickness of the upper Nb electrode of the electron junction from 90 nm to 60 nm. The average current of I/sub c/ was 8800 A/cm/sup 2/, and the measured operating margin of a single gate was +or-32%. At the highest bias level, the average gate delay was 1.5 ps/gate.

Keywords

This publication has 2 references indexed in Scilit:

A Josephson 4b Microprocessor
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1988
A 2.5-ps Josephson or gate
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1987