Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors"

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Abstract
The above paper1presents an approach to the design of fault- tolerant processor arrays. In Section IV of this paper (related work on fault-tolerant networks) the author criticizes a previously published approach presented by Koren [1] and by Gordon, Koren and Silberman [2]. In [1], an algorithm for structuring a linear array on a rectangular grid of processing elements (PE's), some of which may be faulty, is presented. Since similar structuring algorithms for other structures like square arrays and binary trees (in the presence of faulty PE's) are more complicated, a different strategy has been suggested in [1]. According to it, all PE's in the same row or column of the faulty processor will turn into connecting elements (CE's) and will not participate in any future processing task. The remaining PE's still constitute a rectangular grid with one less row and one less column. Consequently, the same structuring algorithms (for fault- free arrays) can be used and in many cases the grid will admit the same size of a binary tree as before [1]. If the communication link between two neighboring processors fails, only the processors within the corresponding single row or column will be declared CE's. In [2], a similar strategy has been applied to hexagonal arrays.

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