Novel packaging of parallel-optical interconnects for high-end servers

1 January 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 4
https://doi.org/10.1109/ofc.2005.193028

Abstract

A novel packaging concept is demonstrated where parallel-optical subassemblies are mounted on the same substrate as processor chips for processor-to-processor communication within a high-end server. A single-channel bit-error ratio <1.5/spl times/10/sup -15/ was measured at 8 Gbit/s.

Keywords

PACKAGING
INTEGRATED CIRCUIT INTERCONNECTIONS
OPTICAL INTERCONNECTIONS
CONNECTORS
BANDWIDTH
AGGREGATES
ROUTING
LABORATORIES
DESIGN OPTIMIZATION
OPEN SOURCE HARDWARE

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