Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors

For gate work function engineering required for ultrathin channel (UTC) double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET), threshold voltage $\left(V_{\mathrm{th}}\right)$ tuning of self-aligned asymmetric $(n^{+}–p^{+})$ DG MOSFETs have been experimentally investigated in comparison with symmetric $(n^{+}–n^{+})$ DG MOSFETs. The vertical UTCs $(12–32\mathrm{nm})$ were fabricated on bulk Si substrates by utilizing the novel ion-bombardment-retarded wet etching and the self-aligned asymmetric DGs were formed by employing the tilted ion implantation and anisotropic dry etching. The fabricated vertical asymmetric DG $n$ -MOSFET with the gate length of $100\mathrm{nm}$ clearly exhibits the desirable $V_{\mathrm{th}}$ of $+0.1\mathrm{V}$ , in addition to the unique DG MOSFET characteristics of the high short-channel-effect immunity with decreasing a channel thickness.