Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM

• 13 November 2002
• proceedings article
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• https://doi.org/10.1109/vlsit.2001.934954

Abstract

Keywords

• VALENCE BAND
• CMOS TECHNOLOGY
• VOLTAGE
• SEMICONDUCTOR DEVICE MODELING
• INTEGRATED CIRCUIT DESIGN
• TUNNELLING
• POWER DISSIPATION
• SILICON ON INSULATOR
• ELECTRON TUNNELING
• ELECTRONS
• TUNNELING
• CYCLE TIME
• ACCESS TIME
• THRESHOLD VOLTAGE