SOI (Silicon-On-Insulator) for High Speed Ultra Large Scale Integration

1 January 1994

journal article
Published by IOP Publishing in Japanese Journal of Applied Physics

Vol. 33 (1S) , 365-369
https://doi.org/10.1143/jjap.33.365

Abstract

Bulk complementary metal-oxide-semiconductor (CMOS) technology scaling can not sustain the historical rate of speed increase. A realistic target for silicon-on-insulator (SOI) delay and power reductions in comparison to bulk technology are 40% and 30%, independent of scaling, mostly through capacitance reduction. Denser isolation allows more compact layout and easy integration of different high speed (E/D NMOS), low power (CMOS), analog (bipolar, grounded-body CMOS) and memory devices. Silicon device speed record (13 ps at 1.5 V, 300 K) has been set with SOI E/D NMOS. Leakage current due to steady state and transient floating-body induced threshold lowering (FITL) is a device issue which deserves more attention.

Keywords

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