This paper presents an approximate analysis of a multiprocessor system consisting of P processors, M memory modules, and B buses. The model assumes constant memory access times, arbitrary memory access patterns, and bus contention. The solution technique aggregates all memories into a composite queue and degrades the service rates of this queue so as to include the effect of bus contention. The throughput predictions from this model are very accurate, typically within 1% of predictions made with either simulation or exact analysis.