Epitaxial VVMOS power transistors

1 February 1980

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 27 (2) , 349-355
https://doi.org/10.1109/T-ED.1980.19867

Abstract

The design aspects of a V-groove vertical-geometry power MOST (VVMOS) using a simple epitaxial-channel technology, are discussed in this paper. The process has several features including ease of fabrication, good threshold voltage controllability, and high breakdown voltage. Expressions for the on-resistance as a function of device parameters and for the device capacitances as a function of the geometric features of the transistor are derived. Experimental results on fabricated devices are presented.

Keywords

GEOMETRY
THRESHOLD VOLTAGE
CAPACITANCE
ELECTRON DEVICES
TECHNOLOGY ASSESSMENT
POWER TRANSISTORS
CONTROLLABILITY
ELECTRICAL RESISTANCE
BREAKDOWN VOLTAGE
FIELD EFFECT TRANSISTOR
FABRICATION
HELIUM

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