A 256K CMOS SRAM with internal refresh
- 23 March 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A four-transistor switched-capacitor load SRAM employing 0.8μm CMOS technology with a cell size of 39.2μm 2 will be reported. The approach makes it possible to access without time-loss for internal refresh. Access time is 43ns and standby power is 3.3μW. Author(s) Hanamura, S. Hitachi Ltd., Tokyo, Japan Minato, O. ; Masuhara, T. ; Sakai, Y. ; Yamanaka, T. ; Moriwaki, N. ; Kojima, F.Keywords
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