Logic simulation system using simulation processor (SP)
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 0738100X,p. 225-230
- https://doi.org/10.1109/dac.1988.14762
Abstract
A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<>Keywords
This publication has 3 references indexed in Scilit:
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- A Digital System Design Language (DDL)IEEE Transactions on Computers, 1968