Fast High-Accuracy Binary Parallel Addition

1 December 1960

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electronic Computers

Vol. EC-9 (4) , 465-469
https://doi.org/10.1109/tec.1960.5219886

Abstract

Future designs of parallel digital computers will be concerned with increased accuracy in arithmetic operations. When the number of bits per operand is increased, one basic speed limitation to these operations is the time required to propagate carries in addition or borrows in subtraction. A quantitative method of evaluating the drastic reduction in time achieved by asynchronous addition techniques is described.

Keywords

DELAY EFFECTS
CONCURRENT COMPUTING
LOGIC TESTING
DIGITAL ARITHMETIC
REGISTERS
COSTS
EQUATIONS
BISMUTH
SIGNAL RESOLUTION

This publication has 1 reference indexed in Scilit:

Fast Carry Logic for Digital Computers
IEEE Transactions on Electronic Computers, 1955