Reducing power dissipation in serially connected MOSFET circuits via transistor reordering
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 614-617
- https://doi.org/10.1109/iccd.1994.331989
Abstract
In this paper we show how transistor reordering based on input signal probabilities can substantially reduce the expected dynamic power dissipation in serially connected MOSFETs. The paper includes a new model for the power dissipation in a MOSFET chain and extensive simulation results. Our results indicate that transistor reordering can significantly reduce the power dissipation in CMOS NAND gates.<>Keywords
This publication has 3 references indexed in Scilit:
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- Performance enhancement of CMOS VLSI circuits by transistor reorderingPublished by Association for Computing Machinery (ACM) ,1993
- Delay analysis of series-connected MOSFET circuitsIEEE Journal of Solid-State Circuits, 1991