Optimizing compilers for the SPARC architecture-an overview
- 1 January 1988
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors discuss the user programming model for the scalable processor architecture (SPARC) and the optimizing compilers for the SPARC-based Sun-4 workstations. They are concerned with two broad areas: how the compilers use the architecture and the design of the compilers themselves. They discuss the registers, synthesized instructions, tagged data support, the compilers, the global and peephole optimizers, and compiler performance analysis.Keywords
This publication has 5 references indexed in Scilit:
- SunOS on SPARCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Integer multiplication and division on the HP precision architectureACM SIGARCH Computer Architecture News, 1987
- Efficient instruction scheduling for a pipelined architecturePublished by Association for Computing Machinery (ACM) ,1986
- DhrystoneCommunications of the ACM, 1984
- Architecture of SOARPublished by Association for Computing Machinery (ACM) ,1984