Delamination cracking in encapsulated flip chips

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Abstract
In this paper, finite element analyses of delamination in flip chip assemblies are described. The objectives of this study were to investigate delamination at the encapsulant/chip interface along the thickness of the chip under thermal loading, and to determine the potential for interconnection failures resulting from this type of delamination. Under operating conditions, the mismatch in thermal expansion between the silicon chip of a flip chip assembly and an organic substrate subjects the solder joints to extremely large strains, which may result in premature failure of the solder connections. Although underfill encapsulation can reduce the strains in the solder joints, it results in the potential for cracking at the chip-underfill-substrate interfaces during temperature cycling. Due to the CTE mismatch, a strong interfacial shear stress concentration develops near the free edge; when this stress exceeds the bonding strength between the encapsulant and the silicon, an interface crack will initiate, may further propagate toward the encapsulated corner of the chip, and then continue along the active face of the chip. Once this adhesion is lost, the solder joints are subjected directly to the strain resulting from the CTE mismatch, and are likely to crack under thermal cycling conditions. In the model, a crack was introduced along the chip edge/encapsulant interface. The crack tip driving force was studied for chips of different sizes. The finite element method was used in the analyses in conjunction with the theory of interfacial fracture mechanics.

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