Solving satisfiability problems using logic synthesis and reconfigurable hardware

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Abstract
This paper presents new results on an approach for solving satisfiability problems (SAT), i.e. creating a logic circuit that is specialized to solve each problem instance on field programmable gate arrays (FPGAs). This approach becomes feasible due to the advances in FPGAs and high-level logic synthesis. In this approach, each SAT problem is automatically analyzed and implemented on FPGAs. We have developed an algorithm which is suitable for implementation on a logic circuit. This algorithm is equivalent to the Davis-Putnam (1960) procedure with a powerful dynamic variable ordering heuristic. The algorithm does not have a large memory structure like a stack, thus sequential accesses to the memory do not become a bottleneck in algorithm execution. Simulation results show that this method can solve a hard random 3-SAT problem with 400 variables within 20 minutes at a clock rate of 1 MHz.

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