Parallel processing of logic module placement
- 1 March 1984
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 20 (5) , 219-220
- https://doi.org/10.1049/el:19840145
Abstract
A parallel-processing algorithm for logic module placement is presented. A pairwise interchange algorithm, directed by the steepest-descent concept, is expanded to the parallel-processing case. By using an AAP (adaptive array processor), it is shown that an N-module placement problem can be processed in 0.06N of the time required by a sequential computer (1 MIPS).Keywords
This publication has 1 reference indexed in Scilit:
- A Placement Algorithm for Array ProcessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983