Efficient ARQ scheme for high error rate channels

8 November 1984

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 20 (23) , 986-987
https://doi.org/10.1049/el:19840671

Abstract

The letter proposes a continuous ARQ scheme, to be used under high error rate conditions. The scheme preserves the ordering of the data blocks and yields a better throughput efficiency—especially for channels with large round-trip delay—than some known comparable schemes, for all block error probabilities larger than 50%.

Keywords

CONTINUOUS ARQ SCHEME
DATA BLOCK ORDERING
PROTOCOL
COMMUNICATION CHANNELS
ERROR CONTROL
LARGE ROUND-TRIP DELAY
HIGH ERROR RATE CHANNELS
THROUGHPUT EFFICIENCY
ERROR DETECTION AND RETRANSMISSION
BLOCK ERROR PROBABILITIES

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